1. Technical Field
The present invention pertains to a router or a switch in a broadband network operating through packet flow forwarding, having a central processor unit (CPU) switched software flow and hardware switched accelerated flow, and a method therefore.
2. Description of the Related Art
A specific type of Access Switching Router (ASR) utilizes an Application Specific Integrated Circuit (ASIC) for packet forwarding in a broadband network, i.e., a hardware solution. The ASIC has limitations in terms of the number of entries in its hardware accelerated forwarding table memory for packet flow. This constitutes a major cause for concern in the design of a broadband router capable of complex network topologies while maintaining wire-speed packet forwarding.
While designing drivers, for example, for a Broadcom 56xx strata-switch forwarding ASIC, all filtering rules were statically inserted in the ASIC. As there were only 1024 rules to utilize, this showed to be a serious limitation, especially when deploying advanced policies and services in the network.
An older version for packet forwarding provided that a router CPU controlled the forwarding through a RAM memory. Such a solution conveys relatively low packet transmission speeds and is not as versatile for the CPU, as the CPU is constantly engaged with other tasks for the router.
A newer generation of routers for flow forwarding introduced hardware accelerated flow forwarding through an ASIC specifically designed for the purpose of flow forwarding in order to discharge the CPU from huge amounts of workload. These ASICS still have to deploy a Content Addressable Memory (CAM) memory with CAM table listings, for example, with as much as 150,000 address entries to other major equipment such as routers, switches, servers, etc. for flow forwarding in the World Wide Web. These memories are very expensive, thus increasing the cost for a router.
The present generation of routers are provided with ASICS, having a small CAM memory which storing capacity is reduced to, for example, 200 addresses. Hence, if there is a lot of traffic only those addresses in the hardware memory would benefit from hardware accelerated flow forwarding and others from CPU software controlled.
In a system with limited hardware accelerated forwarding resources, a complete flow switching cannot be achieved simply because there is not enough space available in the hardware for flow entries. Since hardware acceleration of flows have significant performance advantages to CPU forwarded packets, a lack of hardware resources may lead to performance problems or limit the usability of hardware architectures leading to limited acceleration capabilities.